Flash memory is non-volatile storage device in which data is maintained even when power is removed. It is a technology that is primarily used in portable devices, such as digital cameras, MP3 players, mobile phones, and USB drives, for storage of a large capacity of information. Types of flash memory include NAND types for data storage and NOR types for code storage according to the shape of an electronic circuit inside a semiconductor chip.
In NAND flash memory, cells as storage units are arranged in a vertical direction, and many cells can be made in a narrow space so that a large capacity of information can be stored in NAND flash memory. On the other hand, in NOR flash memory, cells as storage units are arranged in a horizontal direction, and the capacity of data storage is small, and a read speed is fast. Thus, NOR flash memory is primarily used to store core data based on action like in mobile phones. NOR flash memory includes independent address spaces like other memory, and addresses and data buses exist in NOR flash memory to correspond to respective, independent address spaces. Thus, in NOR flash memory, interface with a CPU can be easily performed. However, in NAND flash memory, addresses and data buses use a common bus, and NAND flash memory does not include independent address spaces. Thus, a hardware control logic for solving the problem is needed. In addition, in order to drive a NAND flash memory system, a buffer may be necessarily installed in the hardware control logic.
FIGS. 1 and 2 illustrate the connection relationship between a plurality of conventional NAND flash arrays including data buses containing 8 bits (i.e., the number of input/output (I/O) buses is eight) and data buses containing 16 bits (i.e., the number of I/O buses is sixteen) and a conventional apparatus for controlling the NAND flash arrays.
Conventional NAND flash memory includes 8-bit or 16-bit data I/O buses I/O0 to I/O7 or I/O0 to I/O15. NAND flash memory uses chip enable (CE) signals, command latch enable (CLE) signals, address latch enable (ALE) signals, read enable (RE) signals, and write enable (WE) signals as control input signals for controlling NAND flash memory, and uses ready and busy (R/B) signals as control output signals. In this case, when a NAND flash array includes a plurality of NAND flash, control signals needed are a plurality of CE signals CE0 to CEn, a plurality of R/B signals R/B0 to R/Bn, and common signals CLE/ALE/WE/RE. Thus, as illustrated in FIG. 1, when data I/O buses contain 8 bits, the CLE signals, the ALE signals, the RE signals, and the WE signals are input to each NAND flash memory through a common bus, and the CE signals and the R/B signals are input to each NAND flash memory through respective independent buses. In addition, as illustrated in FIG. 2, when data I/O buses contain 16 bits, 16-bit data buses are constituted by making two NAND flash having 8-bit data buses as a pair.
As described above, the apparatus for controlling NAND flash having the connection relationship with NAND flash memory reads or writes data stored in NAND flash memory through data I/O buses by generating control input signals. In the conventional apparatus for controlling NAND flash, the CPU controls a NAND flash controller in the format of previously-defined commands, and the conventional apparatus for controlling NAND flash controls NAND flash memory by generating NAND flash interface signals. In this case, commands that are previously defined for the CPU to control the NAND flash controller include READ commands, WRITE commands, ERASE commands, INVALID CHECK commands, and WRITE INVALID commands.
In addition, in the conventional apparatus for controlling NAND flash, interface between NAND flash memory including control lines and I/O signal lines and a host processor is constituted by performing the following operations. First, the apparatus for controlling NAND flash receives commands for controlling the operation of flash memory and operation information needed to perform the operation of the commands from the host processor. Next, the apparatus for controlling NAND flash decodes the received commands and operation information and then controls the control lines and the I/O signal lines so that an operation according to the decoded commands can be performed.
However, the conventional control method supports only several limited commands. Thus, there is a limitation in effectively controlling conventional, various types NAND flash. When considering that conventional NAND flash supports a unique operation of NAND flash manufactured by each manufacturer (for example, copy-back program, two-plane page read, cash read), it is difficult to perform an appropriate operation corresponding to NAND flash memory according to various manufacturers. Furthermore, a probability for supporting the unique operation of NAND flash to be newly provided in future is reduced.